Embedded multi-port RAMs have wide-ranging applications in telecommunication and multi-processor systems. Due to the limited access to embedded memories from the external pins of an ASIC, Built-In Self-Test (BIST) is a preferable test for RAMs. Typical BIST algorithms are MARCH algorithm [A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons Ltd., England, 1991] and SMARCH algorithm [B. Nadeau-Dostie, A. Silburt and V. K. Agarwal, "Serial Interfacing for Embedded Memory Testing", IEEE Design and Test of Computers, April 1990, p. 52].
Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed for single-port RAMs. A major problem with this approach is the lack of coverage for some multi-port specific defects, such as inter-port interferences due to shorts across ports.
Modified MARCH algorithms were proposed to detect inter-port shorts by T. Matsumura, "An Efficient Test Method for Embedded Multi-port RAM with BIST Circuitry", Records of the 1995 IEEE Int. Workshop on Memory Tech. Design and Testing, San Jose, Calif., pp. 62-67, 1995, and M. J. Raposa, "Dual Port Static RAM Testing", Proc. IEEE Int. Test Conf., pp. 362-368, 1988. The algorithm tests pairs of ports by simultaneously performing a MARCH test with ascending addresses on one port and another MARCH test with descending addresses on the other port. The test covers all word line shorts and bit line shorts but only within the same row or column. The test may also impose substantial silicon area for routing due to the need to provide different addresses to the two ports.
A paper by S. Wood, R. Gibson, S. Adham, and B. Nadeau-Dostie entitled "A 5 Gb/s 9-Port Application Specific SRAM with Built-In Self-Test", Records of the 1995 IEEE Int. Workshop on Memory Tech. Design and Testing, San Jose, Calif., pp. 68-73, August 1995, discloses shadow write test. In the shadow write test, when a port is placed in shadow write mode, its write drivers continuously force a constant value on all bit lines with its word lines internally disabled. Thus, if no short exists between this port and the port under test, no memory cell will be affected by the shadow write. On the other hand, if an inter-port short does exist, the value read out from the port under test will be affected by the value driven from the shadow write. The shadow write requires design and layout modification.